HDL for Programmable Logic

Code

EEEE4076

School

Electrical & Electronic Engineering

Level

4

Credits

10

Semesters

Autumn Malaysia

Summary

This course will be divided into two: taught material and a hands-on lab exercise
TAUGHT MATERIAL This will contain the following:

HDL overview and latest developments
Latest relevant software from Xilinx and Mentor Graphics
VHDL syntax
VHDL testbench design
Combinational and sequential circuit design
Finite State Machine VHDL design
Hierarchical VHDL design
Parameterised VHDL design
LABORATORY EXERCISE WORK Practical realisation of a digital system will be implemented on a pre-prepared FPGA development board. Marks will be awarded for: quality of code; functionality of the design; written report; plus other parameters to be specified during the course

Target Students

3rd & 4th year students on courses in Electrical and Electronic Engineering: and related courses

Classes

• Two 2-hour lectures each week for 5 weeks
• One 2-hour laboratory each week for 8 weeks

4 hours per week lectures for 5 weeks (20 hours); 8 x 2 hours (approx) lab classes (16 hours); Total =36hrsProject design and write up, and self-study/exam revision (64 hours).

Assessment

• 40% Coursework: HDL design using Xilinx ISE tool, simulator and FPGA
• 60% Exam 1 (2-hour): End semester 2 hours lab based exam

Educational Aims

Learning Outcomes

LO1: Use synthesisable VHDL statements to design medium-complex digital circuits 
LO2: Design VHDL testbench codes for medium complex digital circuits and simulate VHDL codes using a commercial simulator 
LO3: Use synthesisable VHDL statements to design an Industrial bus protocol 
LO4: Design VHDL testbench codes for an Industrial bus protocol and simulate VHDL codes using a commercial simulator 
LO5: Synthesize VHDL codes and then explore implementation into a commercial development board
LO6: Demonstrate an appreciation of the industrial good practice of VHDL/FPGA design for digital circuits

Conveners

• Dr Nandha Kumar Thulasiraman