HDL for Programmable Logic with Project

Code

EEEE4075

School

Electrical & Electronic Engineering

Level

4

Credits

20

Semesters

Full Year Malaysia

Summary

This course will be divided into two: taught material and a hands-on lab exercise
TAUGHT MATERIAL This will contain the following:

HDL overview and latest developments
Latest relevant software from Xilinx and Mentor Graphics
VHDL syntax
VHDL testbench design
Combinational and sequential circuit design
Finite State Machine VHDL design
Hierarchical VHDL design
Parameterised VHDL design
LABORATORY EXERCISE WORK Practical realisation of a digital system will be implemented on a pre-prepared FPGA development board. Marks will be awarded for: quality of code; functionality of the design; written report; plus other parameters to be specified during the course

Target Students

3rd & 4th year MEng and MSc students on courses in Electrical and Electronic Engineering and related discipline

Classes

• One 3-hour practicum each week for 10 weeks
• One 2-hour practicum each week for 8 weeks
• One 2-hour lecture each week for 3 weeks
• Two 2-hour lectures each week for 5 weeks

Autumn:4 hours per week lectures for 5 weeks (20 hours); 8 x 2 hours (approx) lab classes (16 hours); Total =36hrs Spring:2 hours per week lectures for 3 weeks (6 hours); 10 x 3 hours (approx) project lab (30 hours); Total =36hrs Project design and write up, and self-study/exam revision (128 hours).

Assessment

• 10% Coursework 1: HDL design using Xilins ISE tool, simulator and FPGA
• 50% Coursework 2: HDL design project using Xilins ISE tool, simulator and FPGA
• 40% Exam 1 (2-hour): End semester 2 hours lab based exam

Educational Aims

Learning Outcomes

LO1: Use synthesisable VHDL statements to design medium-complex digital circuits 
LO2: Design VHDL testbench codes for medium complex digital circuits and simulate VHDL codes using a commercial simulator 
LO3: Use synthesisable VHDL statements to design an Industrial bus protocol 
LO4: Design VHDL testbench codes for an Industrial bus protocol and simulate VHDL codes using a commercial simulator 
LO5: Synthesize VHDL codes and then explore implementation into a commercial development board
LO6: Demonstrate an appreciation of the industrial good practice of VHDL/FPGA design for digital circuits
LO7: Use synthesisable VHDL statements to design an Industrial digital system application by interfacing an external chip 
LO8: Design VHDL testbench codes for an Industrial digital system application and simulate VHDL codes using a commercial simulator
LO9: Synthesize VHDL codes and then develop stand-alone hardware of the industrial digital system application by realising the design into a commercial development board

Conveners

• Dr Nandha Kumar Thulasiraman