Digital VLSI Design
| Code | School | Level | Credits | Semesters |
| EEEE3125 | Department of Electrical and Electronic Engineerin | 3 | 10 | Spring China |
- Code
- EEEE3125
- School
- Department of Electrical and Electronic Engineerin
- Level
- 3
- Credits
- 10
- Semesters
- Spring China
Summary
This module provides an in-depth understanding of both full and semi-custom CMOS integrated circuit design. It is biased towards electronic systems rather than solid state devices. The module covers:
• CMOS gate DC and transient performance
• CMOS chip fabrication processes
• Analysis of delays in logic gates driving capacitive loads, and their buffering
• VLSI layout design techniques, rules and limitations
• Electrical parameters and measurement of parasitics
• Power dissipation - static and dynamic
• Combinational/Sequential/Peripheral circuit designs
• Custom and semi-custom design styles
• Scaling of integrated circuit dimensions
• Chip yield and economics
• Self-study CAD laboratory exercise with a pre- and post-layout cell design
Reassessment of this module, if required, will be by 100% exam.
Target Students
Part II students on courses offered by Department of Electrical and Electronic Engineering
Classes
- One 1-hour tutorial each week for 12 weeks
- One 2-hour lecture each week for 12 weeks
Assessment
- 25% Coursework 1
- 75% Exam (2-hour)
Assessed by end of spring semester
Educational Aims
This module aims to provide an understanding of semi-custom and full custom design of integrated circuits (IC) for electronic systems. The course is based around the Complementary Metal Oxide Semiconductor (CMOS) integrated circuit process that is used to fabricate the majority of ICs in production today. The content of the module is biased towards design of electronic systems using logic gates rather than solid state devices. Layout design techniques for CMOS logic gates are covered. An understanding of the internals of CMOS ICs will faciliate correct interfacing and choice of clocking strategy. Devices are continually being scaled down in size, hence the term Very Large Scale Integration (VLSI). The effect of such scaling will be discussed and the improvement in various performance factors such as speed and power dissipation will be calculated. This information will allow students to make predictions as to the new circuit performance in years to come.Learning Outcomes
1. Design and analyse digital circuit schematics at the transistor level to the chip level
2. Demonstrate understanding of the physical layout of digital transistor circuits and associated design issues relating to e.g. design rules or performance.
3. Demonstrate understanding of issues related to IC manufacture.
4. Design and analyse a CMOS inverter and digital circuit at the transistor level using the layout design tool
This module contributes to the delivery of the following Engineering Council outcomes:
C1, C2, C3, C4, C5, C14
Conveners
- Dr Sherif Welsen